COA (Computer Organisation and Architecture) 2023

Q1. (a) Why are NAND and NOR gates known as Universal Gates? Realize the Ex-OR function using only NAND gates.

• NAND and NOR gates are considered universal gates because any logical function can be realized using combinations of either NAND or NOR gates alone.
• This property simplifies circuit design and allows for a reduction in the types of gates needed.

(b) Differentiate De-Multiplexer and decoder.

• A De-Multiplexer is a combinational circuit that takes a single input and directs it to one of 2^n possible outputs.
• It has 2^n output lines, where n is the number of select lines.
• For instance, a 1-to-4 De-Multiplexer with two select lines (n=2) can route a single input to one of four output lines.
• The input is directed to one of the output lines based on the binary combination of the select lines.
• De-multiplexers are used in various applications, such as data routing and channel selection.

• A Decoder is a combinational circuit that converts an n-bit binary code into its equivalent decimal or natural binary value.
• It has 2^n output lines and n input lines.
• The number of input lines determines the number of bits in the binary code.
• For example, a 3-to-8 Decoder with three input lines can decode a 3-bit binary input into one of eight output lines.
• Decoders are used in various applications, including address decoding in memory systems and digital display units.

(c) What is the instruction cycle? Draw a flowchart for the instruction cycle of a basic computer.

• The instruction cycle is the process through which a computer fetches, decodes, and executes an instruction.
• It consists of the following stages:
• Fetch: Retrieve the instruction from memory.
• Decode: Interpret the opcode to determine the operation to be performed.
• Execute: Perform the indicated operation.

• The Program Counter (PC) contains the memory address of the next instruction.
• The control unit initiates a memory read operation.
• The instruction at the specified memory address is fetched into the Instruction Register (IR).

1+------------------------+
2|     Instruction Cycle  |
3+------------------------+
4            |
5            v
6+-------------+       +-------------+
7| Instruction | ----> | Increment  |
8|   Fetch     |       |    PC     |
9+-------------+       +-------------+
10            |
11            v
12+-------------+       +-------------+
13| Instruction | ----> | Instruction |
14|   Decode    |       |   Decode    |
15+-------------+       +-------------+
16            |
17            v
18+-------------+       +-------------+
19| Operand     | ----> |   ALU       |
20|   Fetch     |       | Operation  |
21+-------------+       +-------------+
22            |
23            v
24+-------------+       +-------------+
25| Result      | ----> | Result      |
26|  Storage    |       | Storage     |
27+-------------+       +-------------+
28

(d) What is virtual memory and how does it works?

• Virtual memory is a memory management technique that creates the illusion to users of a very large (main) memory.
• It allows the execution of processes that may not entirely fit into physical memory by using a combination of RAM and disk space.

• Page Fault: When a process accesses data not in RAM, a page fault occurs.
• Swap to Disk: The required page is moved from RAM to a designated space on the disk.
• Load into RAM: The needed page is loaded into an available RAM space.
• Continue Execution: The process can now continue execution as if the entire memory is in RAM.

(e) Explain the advantage of SIPO over SISO. Discuss their applications.

• SIPO (Serial-In, Parallel-Out)
• Parallel Output: SIPO allows data to be serially input and then parallelized, providing a parallel output at once.
• Example: Shift registers with SIPO functionality are used to convert serial input data into parallel output.
  
• Reduced Output Delay: Since SIPO provides parallel outputs, the data is available simultaneously, reducing the overall output delay.
• In applications where real-time parallel data processing is crucial, such as in display drivers, SIPO is advantageous for minimizing delays.
• Efficient Data Distribution: SIPO is useful when distributing data to multiple parallel processing units or components.
• Example: In digital-to-analog converters (DACs), SIPO is employed to convert serial digital data into parallel analog signals for multiple channels simultaneously.

• Sequential Output: SISO provides data output sequentially, leading to a delay in obtaining the complete output.
• Example: In applications where real-time parallel data processing is crucial, the sequential nature of SISO can introduce delays and impact overall system performance.
  
• Limited Parallelism: SISO processes data one bit at a time, limiting the parallelism of the output.
  
• Example: In applications requiring simultaneous processing of multiple bits, SISO may not be the most efficient choice.
  
• Complex Parallelization: Achieving parallel output with SISO requires additional components or synchronization, making it more complex.
• Example: In applications where simplicity and ease of implementation are priorities, SIPO is preferred over SISO for parallel data handling.
  
  SIPO Applications: SIPO is beneficial in applications like digital signal processing where parallel data is required at various stages of the processing pipeline.
  
  SISO Applications:
  
  Shift Register: SISO is suitable for basic shift register applications where the focus is on shifting data serially without the need for parallelization.

(f) Design 4-bit Adder-Subtractor.

• A 4-bit adder-subtractor can perform both addition and subtraction on 4-bit binary numbers.
• The design involves combining an adder circuit with a subtractor circuit.
• The subtraction is typically achieved by using two's complement representation.
• for further explanation refer to this video.

Q2. (a) Draw a K-Map and simplify the following expression: (P. Q. R. S)- 2 m (0, 1, 4, 5, 7, 8, 9, 12, 13, 15)

(b) Design a full adder using two half adder and OR gates.

• A full adder can be constructed using two half adders and an OR gate.
• The sum (S) and carry-out (Cout) from the first half adder are fed into the second half adder along with the input bit (B).
• The final sum and carry-out are obtained from the second-half adder.

Q.3 (a) Reduce the following Boolean expression using Boolean laws.

Y-AB+A'B+AB+(AB)' and also design using basic logic gates.

1// Given Boolean Expression
2Y = AB + A'B + AB + (AB)'
3
4// Simplification Using Boolean Laws
5// Identity Law: AB + AB = AB
6// Complement Law: (AB)' = A' + B'
7// Distributive Law: AB + A'B = A + AB
8Y = AB + A + (AB)'
9
10// Further Simplification
11// Applying the Complement Law again
12Y = A + A' + B'
13
14// Applying the Identity Law
15Y = 1 + B'
16
17// Simplifying further
18Y = 1

1// Logic Gate Design
2// A single OR gate with inputs A and its complement A', along with input B' directly connected.
3Y = A + A' + B'

Q3. (b) Design a 3:8 Decoder Design using basic logic gates.

• A 3-to-8 decoder comprises three inputs (A, B, C) and eight outputs (D0 to D7).
• The selection of one of the eight outputs is determined based on the three input signals.
• The truth table illustrates that, given the three input conditions, only one of the outputs (D0 to D7) is activated.

• In this circuit, the three inputs (A, B, C) are decoded into eight outputs, with each output representing a specific combination of the input variables.
• The three NOT gates provide the complement of the inputs, and each of the eight 3-input AND gates generates a corresponding output based on the input combination.

• In a standard J-K flip-flop, there's a potential issue called the "race condition.
• This condition occurs when the inputs J and K change at the same time, leading to a momentary undefined state where the output is unpredictable.

• Initial State: Assume the J-K flip-flop is in the state Q = 0, Q' = 1.
• Simultaneous Input Change: If both J and K change from 0 to 1 simultaneously,
• there's a brief period where the flip-flop may oscillate or move between 0 and 1 before settling on a stable state.

• To overcome the race condition, the Master-Slave J-K flip-flop was introduced.
• It's composed of two interconnected J-K flip-flops, the master and the slave.

• Master Flip-Flop (Positive Edge-Triggered)
• Inputs: J and K Inputs: Accept the external inputs.
• Clock (CLK): Responds only to the rising edge (positive edge) of the clock signal.
• Operation: When the clock signal rises (transition from 0 to 1):
• The J-K flip-flop captures the inputs and enters a temporary or "master" state.
• Outputs (Q and Q') of the master flip-flop are not directly connected to the external outputs.

• Eliminates the race condition by separating the input capture and output presentation phases.
• Ensures that the external outputs are updated only after the master flip-flop has settled.

• The master flip-flop captures the inputs, preventing them from directly affecting the external outputs.
• The slave flip-flop uses the stable master flip-flop outputs to update the external outputs.

Q.4 (b) Design a 3-bit synchronous counter and draw an output waveform.

Q.5 (a) Describe the operation of a 4-bit bidirectional shift register with the help of a block diagram.

Q.5 (b) (b) Realize D-type flip-flop using J-K flip-flop.

Q6. (a) Explain instruction formats and their types using the following expression: X-(A+B)-(C+D)

• Instruction formats are structures that define how instructions are represented in machine language.
• The format includes fields for various components of an instruction, such as the operation code (opcode) and operands.
• X: Represents the destination operand or register.
• A+B: Represents the source operands or registers involved in an operation.
• C+D: Represents another set of source operands or registers.
• Operand Size: The number of bits assigned to each operand.
• Operation Code (Opcode): Specifies the operation to be performed.
• Addressing Modes: Define how operands are specified in an instruction.

• This format typically has three operands or addresses.
• Example: X = A + B - (C + D) can be translated into a three-address instruction format.
• Here, X is the destination, and A, B, C, D are the source operands.

• This format involves two operands or addresses, and one operand serves as both source and destination.
• Example: X = X - (C + D) can be a two-address instruction format. Here, X is both the destination and a source operand.

• This format uses one operand, and the operation is implicitly performed between the operand and the accumulator or a specific register.
• Example: SUB (C + D) can represent a one-address instruction format, where the subtraction is implied with the accumulator.

• Operations are performed explicitly on values from the top of the stack or specific registers without specifying operands in the instruction.
• Example: SUB can be a zero-address instruction format, indicating a subtraction operation without explicitly specifying operands.

• The operation is implied, and operands are understood based on the instruction or opcode.
• Example: X = A + B - (C + D) can be implied as ADD A, B; SUB (C + D).

(b) What is register transfer language? Explain with the help of an example. 

• Register Transfer Language (RTL) is a type of high-level description language used in digital design to describe the flow of data between registers within a digital circuit.
• RTL is used for hardware description and is an abstraction that represents the behavior of a digital system at the register transfer level.
• Registers: RTL focuses on the transfer of data between registers.
• Registers store binary information and serve as temporary storage elements in digital circuits.
• Operations: Describes the operations that are performed on the data during transfer.
• Common operations include addition, subtraction, logical operations, etc.

1// RTL description of a 4-bit adder
2
3// Input registers
4REG A[3:0];  // 4-bit input A
5REG B[3:0];  // 4-bit input B
6
7// Output registers
8REG Sum[3:0];  // 4-bit sum output
9REG Cout;      // Carry-out
10
11// Register transfer operations
12// Perform addition operation
13Sum = A + B;   // 4-bit binary addition
14Cout = A + B;  // Carry-out from addition

• Inputs: A and B are 4-bit input registers.
• Outputs: Sum (4 bits) and Cout are output registers.
• Operations: RTL describes binary addition: Sum = A + B; and captures carry-out: Cout = A + B.
• Abstraction: RTL abstracts binary addition without specifying logic gates.

Q7. (a) Explain the different types of addressing modes in basic computers.

• Addressing modes define how the operands of an instruction are specified in a computer's instruction set architecture.
• Different addressing modes provide flexibility in accessing data and operands in various ways.
• Basic computers typically support a variety of addressing modes to cater to diverse programming requirements.

1LOAD R1, #5; Load register R1 with the immediate value 5

1ADD R1, R2; Add the content of register R2 to register R1

1LOAD R1, M[500]; Load the content of memory location 500 into register R1

1LOAD R1, M[M[100]]; Load the content of the memory location stored in memory location 100 into register R1

1LOAD R1, M[R2]; Load the content of the memory location stored in register R2 into register R1

1LOAD R1, M[R2 + 10]; Load the content of the memory location at the address R2 + 10 into register R1

(b) What is meant by micro-operation? Explain the terms selective set, selective compliment, and selective clear micro-operation.

• In computer architecture, a micro-operation refers to a basic operation performed on the data stored in registers or memory.
• These operations are fundamental to the execution of machine-level instructions and contribute to the overall functionality of a computer's control unit.
• Micro-operations are typically executed in a single clock cycle and are the building blocks of machine-level instructions.

• Selective Set: In a selective set micro-operation, a specific bit or bits in a register are set to 1 while leaving other bits unchanged.
• Selective Complement: In a selective complement micro-operation, a specific bit or
• bits in a register are inverted (changed from 0 to 1 or vice versa) while leaving other bits unchanged.
• Selective Clear: In a selective clear micro-operation, a specific bit or bits in a register are set to 0 while leaving other bits unchanged.

• Control Unit Operation: Micro-operations are often executed by the control unit as part of the fetch-decode-execute cycle.
• Machine Instruction Execution: Micro-operations contribute to the execution of machine-level instructions by manipulating data at the register level.
• Control Signals Generation: Selective micro-operations help generate control signals that determine the behavior of the processor during different phases of instruction execution.

Q8. (a) What is asynchronous data transfer? Explain different methods of asynchronous data transfer.

• Asynchronous data transfer refers to the communication between devices or systems without the use of a shared clock signal.
• Instead, the timing of data transmission is determined by the sender and receiver independently.
• Asynchronous communication is commonly used in various applications, including serial communication between devices.

• Start-Stop Transmission: In start-stop transmission, each character is framed by a start bit and a stop bit.
• The start bit indicates the beginning of the character, and the stop bit marks its end.

1Start Bit | Data Bits | Parity Bit | Stop Bits
2
3-------------------------------------------------
4
50|1101101|1|1

• Baud Rate and Bit Duration: Baud rate represents the number of signal changes per second, indicating the rate of data transmission.
• Bit duration is the time taken for each bit to be transmitted.
• Example: If the baud rate is 9600 bps, the bit duration is 19600​ seconds.

• Asynchronous Parallel Transmission: In parallel transmission, multiple bits are transmitted simultaneously using separate communication lines for each bit.
• Asynchronous parallel transmission involves individual clocks for each data line.

1Data Line 1: | D0 |
2
3Data Line 2: | D1 |
4
5Data Line 3: | D2 |
6
7Data Line 4: | D3 |

• Asynchronous Serial Transmission: Serial transmission involves the sequential transmission of bits over a single communication line.
• In asynchronous serial transmission, start and stop bits frame each character.

1Start Bit | Data Bits | Stop Bits
2
3---------------------------------
4
50|1101101|1

• Asynchronous Parallel/Serial Conversion: Convert parallel data to serial form for transmission and vice versa.
• This is common when connecting parallel devices to serial communication channels.
• Example: Parallel to Serial: Transmitting data from a parallel bus over a serial communication line.
• Serial to Parallel: Receiving data from a serial line and distributing it to multiple parallel lines.

• Flexibility: Asynchronous data transfer allows devices with slightly different clock rates to communicate effectively.
• Simple Implementation: It is relatively straightforward to implement compared to synchronous communication.

(b) What is DMA? Draw and explain the DMA controller in detail.

• DMA (Direct Memory Access) is a feature that allows peripherals or external devices to transfer data from the main memory without involving the CPU.
• DMA is particularly useful for high-speed data transfers, as it offloads the burden from the CPU, allowing it to perform other tasks concurrently.

• DMA Request Lines: Peripheral devices send DMA requests to request access to the memory bus.
• DMA Acknowledge Lines: The DMA controller sends acknowledgment signals to the requesting devices.
• Control Logic: Manages the overall operation of the DMA controller.
• Address Register: Holds the memory address for data transfer.

• DMA Controller Operation: The CPU initializes the DMA controller by setting the memory address, count, mode, and other parameters.
• Peripheral Requests: When a peripheral device requires data transfer, it sends a DMA request.

• DMA Acknowledge: The DMA controller sends an acknowledgment to the requesting device.
• Data Transfer: The DMA controller transfers data between the peripheral device and memory without CPU involvement.
• Interrupt or Notification: Upon completion of the data transfer, the DMA controller can generate an interrupt or notify the CPU.

1+-------------------------------------+
2
3|DMA Controller|
4
5+-------------------------------------+
6
7| DMA Request LinesDMA Ack Lines |
8
9||||
10
11|+-- Bus Arbitration --+||
12
13||||
14
15|Control Logic|||
16
17||||||
18
19| +----+------+----+|||
20
21| | Address Register ||||
22
23| +-----------------+|||
24
25| |Count Register ||||
26
27| +-----------------+|||
28
29| |Mode Register||||
30
31| +-----------------+|||
32
33| |Status Register ||||
34
35| +-----------------+|||
36
37+-----------------------------+||
38
39|CPU Interface||
40

Q9. 1. Cache Memory

2. Auxiliary Memory

• Auxiliary memory, also known as secondary storage, refers to non-volatile storage devices that store data and programs even when the computer is powered off.
• Examples include hard drives, solid-state drives (SSDs), DVDs, and magnetic tapes.

3. Associative Memory

• Associative memory, or content-addressable memory (CAM), allows data retrieval based on content rather than a specific address.
• It compares the content of the data with all stored contents simultaneously, providing quick retrieval.

4. EPROM

• EPROM (Erasable Programmable Read-Only Memory) is a type of non-volatile memory that retains its content even when the power is turned off.
• Unlike ROM, it can be reprogrammed multiple times after exposure to ultraviolet light for erasure.

5. RAM

• RAM (Random Access Memory) is a type of volatile memory that provides high-speed data access to the CPU and stores data that is actively being used by the computer.
• It loses its content when the power is turned off.